A Review on Low Power Optimized Adders Using Nano Field Effect Transistors

DOI

10.2991/978-94-6463-662-8_58How to use a DOI?

Keywords

GNRFET; CNTFET; Adders; MVL

Abstract

This study highlights the positive aspects of GNRFETs and how they could be used to develop simple, fast, and energy-efficient adder circuits. CMOS limitations including drain-induced barrier lowering (DIBL), effects due to length of the channel, elevated leakage current, and temperature-dependent threshold voltage (V_TH), will present challenges for the advancement of future nanotechnology. Nanomaterials, specifically graphene nanoribbons and carbon nano tubes, were employed as the channel materials in two types of FETs- GNRFET (Graphene Nanoribbon Field Effect Transistor) and CNTFET (Carbon Nanotube Field Effect Transistor). Both materials are under investigation as potential alternatives to traditional silicon-based MOSFETs, taking into account their unique properties at the nanoscale. The GNRFET exhibits remarkable electrical characteristics, including carrier mobility, on/off current ratio, and V_TH, indicating substantial potential for advancing MVL logic gates and arithmetic circuits. The application of GNRFET in half and full adders is currently under development and examination in several studies. This review paper analyses half and full adders utilising GNRFETs, focussing on aspects like latency, PDP, and power dissipation. Compared with CMOS logic, digital circuits utilising GNRFET technology demonstrate a significant increase in efficiency. The performance parameters are simulated using HSPICE software.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - A. Parvathi
AU  - S. Nagaraja Rao
PY  - 2025
DA  - 2025/03/17
TI  - A Review on Low Power Optimized Adders Using Nano Field Effect Transistors
BT  - Proceedings of the International Conference on Advanced Materials, Manufacturing and Sustainable Development (ICAMMSD 2024)
PB  - Atlantis Press
SP  - 743
EP  - 752
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-662-8_58
DO  - 10.2991/978-94-6463-662-8_58
ID  - Parvathi2025
ER  -