Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)

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Optimizing D Flip-Flop for 4-bit SRAM Design Using QCA

Authors
V. Bhuvaneswari1, *, S. Yuvaraj1, M. Dishant1, B. Darshan1
1Department of Electronics and Communication Engineering, SRM Institute of Science & Technology, Vadapalani Campus, Chennai, India
*Corresponding author. Email: bhuvanev1@srmist.edu.in
Corresponding Author
V. Bhuvaneswari
Available Online 30 June 2025.
DOI
10.2991/978-94-6463-754-0_69How to use a DOI?
Keywords
Quantum-dot Cellular Automata (QCA); Static Random Access Memory (SRAM); D Flip-Flop; Memory Design; QCA Designer-E
Abstract

In the scientific and engineering domain of nanotechnology, the goal is to make highly efficient devices smaller. Quantum-dot Cellular Automata (QCA) are a new technology that may be used at high speeds with minimal power consumption and a straightforward design. We design a novel 4-bit memory unit in this study, focusing on effective read and write operations. Our effort focuses on designing a high-density, low-power memory tile that can scale for next-generation computer systems. In order to lessen the dynamic performance cost, we employed D flip-flops that were equipped with read/write control cells. Simulation in QCA Designer-E confirm that the revised architecture results in a 16.67% drop in area utilization and a 9% decrease in the total number of cells.These findings demonstrate notable gains in performance and cost-effectiveness, highlighting QCA’s promise as a workable option for cutting-edge, low-power memory systems.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Volume Title
Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)
Series
Atlantis Highlights in Engineering
Publication Date
30 June 2025
ISBN
978-94-6463-754-0
ISSN
2589-4943
DOI
10.2991/978-94-6463-754-0_69How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - V. Bhuvaneswari
AU  - S. Yuvaraj
AU  - M. Dishant
AU  - B. Darshan
PY  - 2025
DA  - 2025/06/30
TI  - Optimizing D Flip-Flop for 4-bit SRAM Design Using QCA
BT  - Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)
PB  - Atlantis Press
SP  - 785
EP  - 798
SN  - 2589-4943
UR  - https://doi.org/10.2991/978-94-6463-754-0_69
DO  - 10.2991/978-94-6463-754-0_69
ID  - Bhuvaneswari2025
ER  -