Optimizing IoT Applications with RTL-Based DMA Controller for Data Transfers

DOI

10.2991/978-94-6463-754-0_66How to use a DOI?

Keywords

Direct Memory Access (DMA); Internet of Things (IoT); Register Transfer Level (RTL); Verilog; data transfer; GDS-II (Graphic Data System)

Abstract

The design and implementation of a Direct Memory Access (DMA) controller for Internet of Things (IoT) applications are examined in this study. Effective data transfers between I/O and memory are made possible by the DMA controller, which lowers CPU load and improves system performance. Making a Register Transfer Level (RTL) model in Verilog specifically for IoT requirements is the first step in the design process. After optimization and synthesis, the final layout is created and then packaged into a GDS-II file for manufacture.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - C. K. Shaila
AU  - M. Jonathan Arthur
AU  - G. Manoj
PY  - 2025
DA  - 2025/06/30
TI  - Optimizing IoT Applications with RTL-Based DMA Controller for Data Transfers
BT  - Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)
PB  - Atlantis Press
SP  - 756
EP  - 764
SN  - 2589-4943
UR  - https://doi.org/10.2991/978-94-6463-754-0_66
DO  - 10.2991/978-94-6463-754-0_66
ID  - Shaila2025
ER  -