Design and Implementation of A Low-Power Modified Mixed-Method Full Adder Architecture Using CMOS Technology

DOI

10.2991/978-94-6463-858-5_234How to use a DOI?

Keywords

modified logic; FA; CMOS; Low power

Abstract

Novel XOR/XNOR and simultaneous XOR-XNOR circuits are suggested in this study. The suggested circuits significantly enhance power consumption and delay thanks to their tiny output capacitance and almost nonexistent short-circuit power dissipation. Additionally, six separate hybrid 1- bit full-adder (FA) circuits designed on the innovative full-swing XOR-XNOR or XOR/XNOR gates are put forth. There are other suggested measures that have their advantages; they include speed, power consumption, power-delay product (PDP), driving ability, and others. Extensive simulations are conducted using Cadence Virtuoso and HSPICE to test the suggested designs. The simulation findings, which were grounded in Tanner’s 16-nm CMOS process technology model, demonstrate that the suggested designs outperform previous FA systems in terms of speed and power efficiency. Our novel approach to transistor size optimization maximizes the circuits’ power-down time (PDT). The suggested approach uses the numerical computing particle swarm optimization technique to get the optimal PDP value with the minimum number of repeats. We analyze the circuit designs by changing the input noise immunity, transistor size, output capacitance, supply voltage, and threshold.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - P. Myna
AU  - R. Mallikarjun
AU  - Potharaju Yakaiah
PY  - 2025
DA  - 2025/11/04
TI  - Design and Implementation of A Low-Power Modified Mixed-Method Full Adder Architecture Using CMOS Technology
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2797
EP  - 2807
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_234
DO  - 10.2991/978-94-6463-858-5_234
ID  - Myna2025
ER  -