Verification and Implementation of Low Power High’ Effective Digital Logic Level Shifter Using 32nm Finfet Technology

DOI

10.2991/978-94-6463-858-5_226How to use a DOI?

Abstract

straightforward layout for the dynamic comparator is created. A key metric in very large scale integration (VLSI) circuits is power consumption. There are a lot of ways to lower the circuit’s power usage have been suggested before. Presented here is a FINFET comparator that makes use of a dynamic latch; this design is well-suited for use in high-speed, low-power Analog-to-Digital Converters (ADCs). The Flash type ADC is where this idea is meant to be suggested. The characteristics of both the differential current detecting comparator and the resistive isolating comparator are brought together in this circuit. Utilizing 32nm FINFET technology, the design has been executed in LT SPICE and HSPICE. The simulation findings were confirmed using three different supply voltages: 1.6V, 1.8V, and 2.0V. According to the current findings, 1.6V has the shortest propagation delay at 0.715 ns but the highest power dissipation at 0.7899 mW. The 2.0V supply, on the other hand, had a shorter delay of 0.550 ns and generated 1.471 mW. Flash ADC, differential current sensing comparator, FINFET, and dynamic latch comparator are all terms included in the index.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Raikota. Kavya
AU  - Y. David Solomon Raju
PY  - 2025
DA  - 2025/11/04
TI  - Verification and Implementation of Low Power High’ Effective Digital Logic Level Shifter Using 32nm Finfet Technology
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2713
EP  - 2720
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_226
DO  - 10.2991/978-94-6463-858-5_226
ID  - Kavya2025
ER  -