Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

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Parallel Pixel Processing And Filtering Architectures For Image Processing In Verilog For Real-Time Applications

Authors
Sirasanagandla Bhavyesh1, *, Akshay Kondru1, Saliganti Yashwanth1, K. Jamal1, Kiran Mannem1, M. Suneetha1
1Department of Electronics and Communication Engineering, Gokaraju Rangaraju Institute of Engineering and Technology (GRIET), Hyderabad, Telangana, India
*Corresponding author. Email: bhavykun@gmail.com
Corresponding Author
Sirasanagandla Bhavyesh
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_207How to use a DOI?
Keywords
Parallel Processing; AXI; Pixel Caches; FSM; Hardware acceleration
Abstract

Parallel Pixel Processing and Filtering Architectures for Image Processing in Verilog (PPPFA). The article discusses image processing using hardware acceleration with focus on the systems which process grayscale images independently of color images. The architecture for processing grayscale images applies 512 × 512 grayscale image processing by spatial convolution-based filtering and edge detection with optimizations based on parallelism, pixel caching, and AXI4-based DMA to ensure fast data movement. For chromatic images, a Verilog-based implementation processes two pixels concurrently with a custom state machine accepting an input of 768x512 pixel image. It carries out operations such as addition and subtraction of brightness, thresholding, inversion, and black-and-white conversion to facilitate effective real-time image manipulations.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_207How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - Sirasanagandla Bhavyesh
AU  - Akshay Kondru
AU  - Saliganti Yashwanth
AU  - K. Jamal
AU  - Kiran Mannem
AU  - M. Suneetha
PY  - 2025
DA  - 2025/11/04
TI  - Parallel Pixel Processing And Filtering Architectures For Image Processing In Verilog For Real-Time Applications
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2478
EP  - 2493
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_207
DO  - 10.2991/978-94-6463-858-5_207
ID  - Bhavyesh2025
ER  -