Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

<Previous Article In Volume
Next Article In Volume>

Design of Ternary Logic gates and Arithmetic Circuits to Enhance Energy Efficiency using CNTFET Technology

Authors
K. Jathin Krishna1, *, S. V. Ratan Kumar1, J. Sofia Priya Dharshini1, B. Himabindu1, B. Dinesh1, B. Krupakar1
1Department of Electronics and Communication Engineering, RGMCET, Nandyal, AP, India
*Corresponding author. Email: jathin9581@gmail.com
Corresponding Author
K. Jathin Krishna
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_190How to use a DOI?
Keywords
Ternary logic; PDP; CNTFET; STI; MVL
Abstract

In modern electronic systems, the growing demand for higher information density and faster processing speeds requires advanced logic technologies. So multi-valued logic (MVL) introduces, it serves as alternative to binary logic schemes. The paper explores the new proposed novel circuit designs including CNTFET-STI, TNAND, TNOR, aimed at minimizing energy consumption as measured by the power-delay product (PDP) Furthermore, the proposed three-valued logic circuits perform basic arithmetic operations. To check proper functionality and behaviour of circuits that are taken under simulations with Synopsys HSPICE with integration of 32 nm Stanford model of CNTFET. Outcome of the results indicate that designs are using low PDP and power usage. The proposed circuits resulting in an overall 98% improvement in PDP.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

<Previous Article In Volume
Next Article In Volume>
Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_190How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - K. Jathin Krishna
AU  - S. V. Ratan Kumar
AU  - J. Sofia Priya Dharshini
AU  - B. Himabindu
AU  - B. Dinesh
AU  - B. Krupakar
PY  - 2025
DA  - 2025/11/04
TI  - Design of Ternary Logic gates and Arithmetic Circuits to Enhance Energy Efficiency using CNTFET Technology
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2279
EP  - 2294
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_190
DO  - 10.2991/978-94-6463-858-5_190
ID  - Krishna2025
ER  -