Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

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Energy-Efficient Contention-Free 25-Transistor Single-Phase Clocked Flip-Flop in 45nm CMOS

Authors
B. Nazma1, *, G. Ganga Dharani1, E. Hemanth1, G. Madhusudhan1, K. Yashodha1
1Department of Electronics and Communication Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, India
*Corresponding author. Email: nazma435.billa@gmail.com
Corresponding Author
B. Nazma
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_193How to use a DOI?
Keywords
Ultra-low power; Static; Flip-flop; 45 nm technology
Abstract

To significantly enhance energy efficiency in sequential digital circuits, this project will develop an ultralow power true single-phase clocked (TSPC) flip-flop using a novel 25-transistor design, expandable to 29 transistors with a reset function. By eliminating redundant charge and discharge cycles, the flip-flop will drastically reduce power consumption. Transistor-level optimization will be utilized to address floating nodes, ensuring a fully static and contention-free operation within 55 nm CMOS technology. This innovative flip-flop design will be a crucial component in various digital systems, particularly in applications where minimizing power consumption is essential, such as battery-operated devices, IoT systems, and wearable technology. Additionally, it will cater to the growing demand for energy-efficient components in large-scale digital infrastructures like data centers and mobile computing platforms, where optimizing power usage is vital for enhancing overall system performance and sustainability.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_193How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - B. Nazma
AU  - G. Ganga Dharani
AU  - E. Hemanth
AU  - G. Madhusudhan
AU  - K. Yashodha
PY  - 2025
DA  - 2025/11/04
TI  - Energy-Efficient Contention-Free 25-Transistor Single-Phase Clocked Flip-Flop in 45nm CMOS
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2316
EP  - 2325
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_193
DO  - 10.2991/978-94-6463-858-5_193
ID  - Nazma2025
ER  -