Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

High Speed Energy Efficient Dynamic Logic One Trit Multiplier Using CNTFET

Authors
S. V. Ratankumar1, *, G. Hemanthkumar1, S. Shivarekha1, Pranathi1, Y. Santhosh1
1Dept. Of ECE, RGMCET, Nandyal, AP, India
*Corresponding author. Email: saneratankumar@gmail.com
Corresponding Author
S. V. Ratankumar
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_229How to use a DOI?
Keywords
Carbon nanotubes; Multivalued logic; Dynamic ternary Multiplier
Abstract

Multi-valued logic systems were first conceived to solve connection problems with conventional binary circuits. Ternary logic offers the advantages of minimum circuit complexity, lower power consumption, and a more compact chip design. To further improve these advantages, this project presents a novel ternary 1-trit multiplier circuit based on clocked dynamic and pass transistor logic. The proposed design significantly reduces transistor count, requiring only 28 transistors, which eliminates the need for conventional logic gates, encoders/decoders, and multiplexers. By making the circuit design simpler, this method significantly cuts down on power use, delays, and improves overall performance compared to the latest designs out there. Simulations were conducted using the Stanford 32-nm CNTFET model file and the Synopsys HSPICE simulator at a supply voltage of 0.9 V.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_229How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

TY  - CONF
AU  - S. V. Ratankumar
AU  - G. Hemanthkumar
AU  - S. Shivarekha
AU  - Pranathi
AU  - Y. Santhosh
PY  - 2025
DA  - 2025/11/04
TI  - High Speed Energy Efficient Dynamic Logic One Trit Multiplier Using CNTFET
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2744
EP  - 2754
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_229
DO  - 10.2991/978-94-6463-858-5_229
ID  - Ratankumar2025
ER  -