FinFET Technology based Low-Delay Evaluation of a 3-bit Vedic Multiplier MAC Unit

DOI

10.2991/978-94-6463-858-5_144How to use a DOI?

Keywords

Multiply-and-Accumulate Unit (MAC); Carry Save Adder (CSA); Parallel-in-Parallel-out (PIPO); Complementary Metal-Oxide-Semiconductor (CMOS); D-Latch; Vedic Multiplier; Fin Field Effect Transistor (FinFET); Transmission gates; Full adder; Half adder; Power; Delay; Cadence EDA (Electronic Design Automation)

Abstract

This work represents the Development and realization on 3-bit Vedic Arithmetic Multiplier anchored in MAC Unit in FinFET Technology. Nowadays for designing any Integrated Circuit, Delay and power should be low to make IC more advantageous. We opted for FinFET Technology because of its advantages over CMOS.As in FinFET the leakage is lessen, it has 3D structure and also it has good control on its Channel. As Vedic Multiplication gives faster results than traditional Multiplication also it is time saving process. Carry save Adder (CSA) is very advantageous than other adders as its time delay and avg. Power are very low and CSA is more efficient. MAC is mainly used in DSP applications. To implement MAC, we integrated Vedic Multiplier, Carry save Adder (CSA), full parallel sequential register. Throughout research, delay- power measures examined alongside between CMOS and FinFET.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - A. Adinarayana
AU  - T. Swathi
AU  - S. Sagar
AU  - K. Sai Mokshith
PY  - 2025
DA  - 2025/11/04
TI  - FinFET Technology based Low-Delay Evaluation of a 3-bit Vedic Multiplier MAC Unit
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 1779
EP  - 1789
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_144
DO  - 10.2991/978-94-6463-858-5_144
ID  - Adinarayana2025
ER  -