Design and Implementation of Binary Ring LWE Accelerator

DOI

10.2991/978-94-6463-858-5_153How to use a DOI?

Keywords

Binary Ring-LWE; Hardware Accelerator; Carry-save Adder; carry look ahead adder

Abstract

This work introduces an optimized hardware accelerator for Binary Ring-LWE-based cryptographic operations, designed to improve performance, security, and scalability. The architecture utilizes Carry Look ahead Adders (CLA) for faster modular arithmetic, AND-accumulator logic for efficient multiplication, and Circular Shift Registers (CSRs) for parallel data processing. A centralized Control Unit (CU) manages the execution flow, ensuring synchronized operations, while the decryption mechanism extracts Most Significant Bits (MSBs) to maintain accuracy and security.

To strengthen hardware security, the design includes countermeasures against power and timing side-channel attacks, reducing potential vulnerabilities. Additionally, the architecture is highly modular and scalable, allowing it to adapt to varying cryptographic workloads without compromising efficiency. The combination of optimized arithmetic units, efficient data flow, and robust security mechanisms makes this accelerator well-suited for hardware-based lattice cryptography, providing a fast, secure, and resource-efficient solution for modern cryptographic applications in embedded and high-performance computing environments.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - K. Nithya
AU  - O. Divya
AU  - G. Vishwajit Srikrishna
AU  - Sangeeta Singh
PY  - 2025
DA  - 2025/11/04
TI  - Design and Implementation of Binary Ring LWE Accelerator
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 1868
EP  - 1875
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_153
DO  - 10.2991/978-94-6463-858-5_153
ID  - Nithya2025
ER  -