Systematic Analysis on TPU’s History and Key Technologies Behind It
- DOI
- 10.2991/978-94-6463-986-5_46How to use a DOI?
- Keywords
- TPU; Systolic Array; Machine Learning; Deep Learning
- Abstract
With the rapid growth of artificial intelligence and deep learning, traditional computing architectures face limitations in efficiency and scalability. This paper explores Google’s Tensor Processing Unit (TPU) to understand how specialized hardware accelerates AI workloads and drives next-generation computational innovations. This article analysis the development and key technologies behind Google’s TPU. It begins by explaining how Google created the TPU to meet rising computational demands for deep learning, which CPUs and GPUs could not efficiently handle. The paper outlines the main components of a TPU, such as the systolic array, high-bandwidth memory, and matrix multiply unit. It then traces the evolution of TPU versions from v1 to v4, highlighting improvements in speed, cooling, and scalability. Key technologies like matrix multiplication optimization, low-precision computing, and the use of TensorFlow are also discussed. Finally, the impact of TPUs on both Google’s services and broader AI research is summarized, showing how they make high-performance computing more accessible and efficient.
- Copyright
- © 2026 The Author(s)
- Open Access
- Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.
Cite this article
TY - CONF AU - Yilin Zhao PY - 2026 DA - 2026/02/18 TI - Systematic Analysis on TPU’s History and Key Technologies Behind It BT - Proceedings of the 2025 International Conference on Electronics, Electrical and Grid Technology (ICEEGT 2025) PB - Atlantis Press SP - 450 EP - 457 SN - 2352-5401 UR - https://doi.org/10.2991/978-94-6463-986-5_46 DO - 10.2991/978-94-6463-986-5_46 ID - Zhao2026 ER -