Implementation of Clock Network Based on Clock Mesh

DOI

10.2991/icitmi-15.2015.123How to use a DOI?

Keywords

Clock Tree Synthesis; Clock Mesh; Clock Skew; On-chip Variation

Abstract

Clock network synthesis is an important part of digital integrate circuit design. For the purpose of further reducing the effect of clock skew and On-chip Variation, this paper realized a clock mesh structure by using Encounter EDI tool basing on traditional clock tree synthesis. Experiment results validated the advantage of clock mesh in clock skew optimizing and On-chip Variation.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xin He
AU  - Xu Huang
AU  - Yujing Li
PY  - 2015/10
DA  - 2015/10
TI  - Implementation of Clock Network Based on Clock Mesh
BT  - Proceedings of the 4th International Conference on Information Technology and Management Innovation
PB  - Atlantis Press
SP  - 739
EP  - 744
SN  - 2352-538X
UR  - https://doi.org/10.2991/icitmi-15.2015.123
DO  - 10.2991/icitmi-15.2015.123
ID  - He2015/10
ER  -