AI-Driven Back-End Design of Digital Integrated Circuits

DOI

10.2991/978-94-6463-821-9_51How to use a DOI?

Keywords

Logic Synthesis; Deep Reinforcement Learning; Placement; Clock Tree Synthesis

Abstract

This paper investigates the critical applications of Artificial Intelligence (AI) in the back-end design of digital integrated circuits, with a specific focus on logic synthesis, placement and routing, and clock tree synthesis (CTS). As the integration density of digital circuits increases and process node advancements approach physical limitations, traditional back-end design faces challenges such as complex layout optimization, multi-dimensional power management, and difficulties in timing closure. Deep Reinforcement Learning (DRL) has seen rapid development in recent years, and AI technology has significantly improved design efficiency and quality through data-driven and intelligent automation methods. In placement and routing, DRL and Generative Adversarial Networks (GANs) have enabled rapid optimization, with Google’s AI tools saving thousands of human hours in chip layout. In logic synthesis, reinforcement learning frameworks (such as A2C and ERL) and active learning strategies (such as Bulls-Eye) have improved circuit area and power optimization. In CTS, GAN-driven prediction models have reduced the number of clock buffers by 31%. AI technology promotes the intelligence and efficiency of digital chip back-end design through automation, global optimization, and efficient design space exploration, and it is expected to further integrate with EDA tools in the future.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Jiakang Li
PY  - 2025
DA  - 2025/08/31
TI  - AI-Driven Back-End Design of Digital Integrated Circuits
BT  - Proceedings of the 2025 2nd International Conference on Mechanics, Electronics Engineering and Automation (ICMEEA 2025)
PB  - Atlantis Press
SP  - 502
EP  - 510
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-821-9_51
DO  - 10.2991/978-94-6463-821-9_51
ID  - Li2025
ER  -