FPGA-Based Hardware Accelerator Design for Convolutional Neural Networks

DOI

10.2991/978-94-6463-821-9_74How to use a DOI?

Keywords

CNN; Hardware Accelerator; FPGA

Abstract

In recent years, convolutional neural networks (CNNs) have achieved groundbreaking progress in the field of computer vision. However, the computational complexity and storage requirements of CNN models pose significant challenges for deployment on embedded systems and edge devices, with traditional CNN algorithms making it challenging for the author to implement hardware designs for more complex models. Currently, there is an urgent need for hardware optimization and acceleration to meet the growing demands of artificial intelligence development. This paper systematically reviews the latest research advances in FPGA-based CNN hardware accelerators, focusing on the analysis of hardware-friendly algorithmic optimizations and efficient hardware architecture designs. The author conducts a comprehensive discussion from both hardware and software perspectives, summarizing various acceleration and optimization methodologies. By comparing research findings from multiple representative papers, the author synthesizes the performance of different acceleration approaches in terms of computational efficiency, resource utilization, and energy efficiency ratio, while contrasting their acceleration advantages across different platforms. Furthermore, the author discusses the current challenges faced in this domain and provides insights into potential future research directions.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Jiayan Chen
PY  - 2025
DA  - 2025/08/31
TI  - FPGA-Based Hardware Accelerator Design for Convolutional Neural Networks
BT  - Proceedings of the 2025 2nd International Conference on Mechanics, Electronics Engineering and Automation (ICMEEA 2025)
PB  - Atlantis Press
SP  - 765
EP  - 775
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-821-9_74
DO  - 10.2991/978-94-6463-821-9_74
ID  - Chen2025
ER  -