Comparation of Common-Centroid and Interdigitated Layout Techniques for Two-Stage CMOS Amplifier Optimization Based on Cadence Virtuoso

DOI

10.2991/978-94-6463-821-9_95How to use a DOI?

Keywords

Common-Centroid Layout; Interdigitated Latout; Cadence Virtuoso

Abstract

In the design of analogue integrated circuit, layout optimization is essential for achieving higher performance, reliability, and yield. The study presents a comprehensive comparation of two dominant layout techniques, which are common-centroid and interdigitated, applied to the optimization of two-stage CMOS amplifier based on Cadence Virtuoso. The analysis explores the theoretical principles of each method, investigating how symmetric arrangements in common-centroid layouts decrease linear process gradients and balance parasitic components, while interdigitated layouts improve local matching and thermal coupling through changing transistor placements. Practical implementation challenges, which include increased routing complexity, silicon area requirements and additional parasitic effects, are discussed with recent advances like improved segmentation algorithms and automated layout segmentation tools. The study also explores iterative optimization strategies, sensitivity analyses to process variations and hybrid layout approaches that combine the advantages of both technologies. Finally, new technologies like machine learning–based layout optimization are considered for performance improvements in future, which offer new solutions to satisfy the stricter demands of modern CMOS technologies.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Zihan Gao
PY  - 2025
DA  - 2025/08/31
TI  - Comparation of Common-Centroid and Interdigitated Layout Techniques for Two-Stage CMOS Amplifier Optimization Based on Cadence Virtuoso
BT  - Proceedings of the 2025 2nd International Conference on Mechanics, Electronics Engineering and Automation (ICMEEA 2025)
PB  - Atlantis Press
SP  - 987
EP  - 994
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-821-9_95
DO  - 10.2991/978-94-6463-821-9_95
ID  - Gao2025
ER  -