Design and Implementation of RISC-V Based Convolutionally Accelerated Processors

DOI

10.2991/978-94-6463-821-9_43How to use a DOI?

Keywords

RISC-V; Accelerator; System-on-Chip

Abstract

Convolutional neural networks (CNNs) have become widely used in a variety of application scenarios due to the rapid development of deep learning and artificial intelligence technologies. However, traditional general-purpose processors face performance bottlenecks when dealing with large-scale convolutional operations. Specifically, the Reduced Instruction Set Computer V (RISC-V) open-standard design is utilized in many publicly accessible implementations and has been warmly embraced by the international community of researchers and business users. In this paper, the author propose a system-on-chip (SOC) design depending on the RISC-V instruction set architecture, which significantly improves the efficiency of convolutional operations by extending the custom instruction set and integrating a dedicated AI computation unit (AI Core). The architectural design, module partitioning, sub-module implementation, and simulation results of the processor are described in detail in this paper. According to the experimental results, the design maintains high accuracy when running the Yolv4 small model while achieving a 10x speedup in convolutional operations when compared to conventional CPU serial operations.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Zhekai Cui
PY  - 2025
DA  - 2025/08/31
TI  - Design and Implementation of RISC-V Based Convolutionally Accelerated Processors
BT  - Proceedings of the 2025 2nd International Conference on Mechanics, Electronics Engineering and Automation (ICMEEA 2025)
PB  - Atlantis Press
SP  - 413
EP  - 424
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-821-9_43
DO  - 10.2991/978-94-6463-821-9_43
ID  - Cui2025
ER  -