Design of Asynchronous FIFO with Adjustable Input/Output Bit Width Based on Verilog

DOI

10.2991/978-94-6463-821-9_70How to use a DOI?

Keywords

Asynchronous FIFO; Cross-Clock Domain; Bit-Width Conversion; Data Width Adaptation

Abstract

An asynchronous First-In-First-Out (FIFO) is a fundamental data storage and buffering mechanism designed to operate across different clock domains, where the read and write operations are driven by separate, and asynchronous clock sources. This characteristic makes asynchronous FIFOs an essential component for enabling reliable data transmission between circuits with mismatched or independent clocks. The primary focus of this study, implemented in Verilog, is the design, development, and evaluation of an asynchronous FIFO tailored to address challenges in cross-clock domain communication. In addition to supporting the standard FIFO operations, this work introduces an innovative bit-width conversion function. This function allows the FIFO to adapt to varying data requirements by either concatenating or truncating data based on the target application’s needs. Such a feature significantly enhances the FIFO’s flexibility, enabling it to accommodate diverse data sizes and formats, particularly in complex systems. Furthermore, the modified FIFO is optimized for high-speed data transfers and ensures compatibility between systems that utilize differing data widths, broadening its applicability. These improvements position the asynchronous FIFO as a versatile and efficient solution for advanced cross-clock domain data management in modern digital systems.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Langhe Tian
PY  - 2025
DA  - 2025/08/31
TI  - Design of Asynchronous FIFO with Adjustable Input/Output Bit Width Based on Verilog
BT  - Proceedings of the 2025 2nd International Conference on Mechanics, Electronics Engineering and Automation (ICMEEA 2025)
PB  - Atlantis Press
SP  - 730
EP  - 737
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-821-9_70
DO  - 10.2991/978-94-6463-821-9_70
ID  - Tian2025
ER  -