Memristor Based Subtractors and Comparators for Efficient MUX Design in In-Memory Computing Systems

DOI

10.2991/978-94-6463-718-2_137How to use a DOI?

Keywords

CMOS-based architectures; memristor-based subtractors; n-bit subtractor; Digital Subtractors; Memristor-Based Comparators; Tanner

Abstract

Memristor-based computing had emerged as a transformative alternative to conventional CMOS-based architectures, offering unparalleled advantages Regarding the area efficiency, energy usage and computational velocity. This research delves into the design and optimization of memristor-based subtractors, comparators, and multiplexers (MUX), employing a hybrid framework that integrates analog and digital memristive computing principles. Addressing the limitations of existing n-bit subtraction methods—such as high memristor count, sequential delays, and architectural complexities—a novel approach leveraging Memristor-Aided Logic (MAGIC) and advanced material innovations is proposed. The proposed designs capitalize on memristor properties, including resistance variability and non-volatility, to achieve enhanced analog efficiency, compactness, and high-speed performance. Subtractors and comparators utilize hybrid analog-digital configurations, while MUX designs incorporate memristor-based switching mechanisms for low-power, high-performance operations. Advances in memristor fabrication, including metal-oxide and 2D materials, further enhance logic gate performance, contributing to reduced computational steps, resource utilization, and operational stability. Tanner EDA supports waveform probing, circuit simulation, schematic entry, and layout editing, featuring tools like S-Edit, T-Spice, and L-Edit for efficient IC development. The software enables behavioral modeling across abstraction levels, cross-probing, and seamless integration with simulators like AFS, Eldo, and Questa ADMS for co-simulation. File system configurations in Tanner adopt a YAML-like format, supporting essential modules such as SQLI, PHPFOX, Redis, and Docker, and facilitating customizable setups. Coding implementations highlight the transition from base designs using Tanner’s EDIF (Electronic Design Interchange Format) to advanced configurations, incorporating performance metrics like TRAN_Measure for rise time and pulse width simulations. Experimental results validate the efficacy of the proposed designs and Tanner’s tools, demonstrating precise, scalable, and optimized solutions for in-memory computing and analog IC development. These advancements underscore the potential of the proposed framework to redefine scalable, energy-efficient computing architectures for future applications.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - A. Vasantharaj
AU  - R. Vigneshwari
PY  - 2025
DA  - 2025/05/23
TI  - Memristor Based Subtractors and Comparators for Efficient MUX Design in In-Memory Computing Systems
BT  - Proceedings of the International Conference on Sustainability Innovation in Computing and Engineering (ICSICE 2024)
PB  - Atlantis Press
SP  - 1642
EP  - 1654
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-718-2_137
DO  - 10.2991/978-94-6463-718-2_137
ID  - Vasantharaj2025
ER  -