Performance Analysis of Differential and Single Ended SRAM Cells in Low Power Smart System Applications

DOI

10.2991/978-94-6463-716-8_67How to use a DOI?

Keywords

SRAM; Low Power Design; Internet of Things; System on Chip; Delay; Static Noise Margin; Security

Abstract

Smart systems, including IoT devices and biometric authentication platforms performance, depend on internal memory architecture for its high-speed, low-power operation and reliable data storage. As modern CMOS technology advances, minimizing leakage current and ensuring data retention have become critical challenges. This research investigates and compares the delay, power dissipation, and noise margin of 6T (differential mode) and 8T (single-ended) SRAM cells. While 6T SRAM remains the industry standard for general-purpose memory, 8T SRAM demonstrates superior read stability and reduced leakage, making it suitable for low-power applications. Comparative analysis reveals that the 8T SRAM offers a higher read noise margin than the 6T cell. Read delay of 8T and 6T 2.3ns and 23.4ps respectively. The write delay for the 6T cell is 481ps, compared to 1.8ns for the 7T cell. Simulations were conducted using 90nm CMOS technology across a supply voltage range of 300mV to 1Volt. In this work, we consider two methods for calculating stability: the Butterfly Curve and the N-Curve method. This study highlights the potential of SRAM Memory designs in shaping future technologies like IoT, AI accelerators, and low-power smart systems by optimizing critical parameters such as power consumption, security, and silicon area.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Sneha Nagar
AU  - Vaibhav Neema
AU  - Ashish Panchal
AU  - Priyanka Sharma
PY  - 2025
DA  - 2025/05/26
TI  - Performance Analysis of Differential and Single Ended SRAM Cells in Low Power Smart System Applications
BT  - Proceedings of the International Conference on Recent Advancements and Modernisations in Sustainable Intelligent Technologies and Applications (RAMSITA 2025)
PB  - Atlantis Press
SP  - 905
EP  - 913
SN  - 1951-6851
UR  - https://doi.org/10.2991/978-94-6463-716-8_67
DO  - 10.2991/978-94-6463-716-8_67
ID  - Nagar2025
ER  -