Absolute Value Detector with Minimized Delay and Energy in Integrated Circuits

DOI

10.2991/978-94-6463-864-6_42How to use a DOI?

Keywords

Absolute Value Detector; 2’S Complement; Comparator; Logical Effort

Abstract

This paper presents the comprehensive design, optimization, and validation of a 5-bit absolute value detector (AVD), achieving notable reductions in delay and energy consumption for digital integrated circuits. AVDs are crucial in applications such as digital signal processing and numerical comparisons, converting signed binary numbers to magnitude-only values. Leveraging the efficiency of two’s complement representation, the proposed architecture integrates a 4-bit binary adder with a 4-to-1 multiplexer, dynamically selecting between the original input and its two’s complement based on the sign bit. A comparator optimized through Karnaugh map simplification significantly reduces transistor count and switching activity, enhancing energy efficiency. Critical path delay optimization is systematically achieved using Logical Effort theory, resulting in an approximate stage effort of 1.836 and a total estimated delay of 127.5 ns. Energy consumption, evaluated through datasheet analysis and gate sizing, is estimated at about 3 nJ per operation, indicating strong suitability for low-power applications. Extensive simulation and validation, performed with SystemVerilog testbenches and visualized using GTKWave, confirm close alignment with theoretical predictions. This optimized circuit approach effectively balances performance and power consumption, providing a scalable foundation for integration into advanced digital systems.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Rongxin Li
PY  - 2025
DA  - 2025/10/23
TI  - Absolute Value Detector with Minimized Delay and Energy in Integrated Circuits
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 453
EP  - 463
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_42
DO  - 10.2991/978-94-6463-864-6_42
ID  - Li2025
ER  -