Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)

<Previous Article In Volume
Next Article In Volume>

Advancements in STT-MRAM Circuit Design for Enhanced Write Efficiency and Reliability

Authors
Zhenyu Liu1, *
1School of Microelectronics, South China University of Technology, Guangzhou, China
*Corresponding author. Email: 202364830211@mail.scut.edu.cn
Corresponding Author
Zhenyu Liu
Available Online 23 October 2025.
DOI
10.2991/978-94-6463-864-6_29How to use a DOI?
Keywords
STT-MRAM; Write driver circuits; Write self-termination circuits; Word line driver circuits; Peripheral auxiliary circuits
Abstract

STT-MRAM excels with fast reads, low write power, and high endurance, making it a key focus in emerging non-volatile memory research. However, write randomness, different P and AP write times, and temperature fluctuations challenge write efficiency and reliability. Fixed write cycle designs ensure state switching but waste power. This paper examines optimized write self-termination, write driver, word line driver, and peripheral auxiliary circuits for write. Write self-termination circuits save energy by detecting MTJ resistance changes to stop the write operation early. They each have advantages in terms of area, sensing margin, and speed, but they cannot balance all of them. In addition, in high-density and high-capacity storage, the parasitic capacitance effect and IR drop will reduce the drive ability of the write driver circuit. So this article also studies the write drive circuit, word line drive circuit, and peripheral auxiliary circuit to improve the write drive ability.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

<Previous Article In Volume
Next Article In Volume>
Volume Title
Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
Series
Advances in Engineering Research
Publication Date
23 October 2025
ISBN
978-94-6463-864-6
ISSN
2352-5401
DOI
10.2991/978-94-6463-864-6_29How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - Zhenyu Liu
PY  - 2025
DA  - 2025/10/23
TI  - Advancements in STT-MRAM Circuit Design for Enhanced Write Efficiency and Reliability
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 277
EP  - 288
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_29
DO  - 10.2991/978-94-6463-864-6_29
ID  - Liu2025
ER  -