Digital Circuit Acceleration Techniques for Computer Vision Tasks

DOI

10.2991/978-94-6463-864-6_16How to use a DOI?

Keywords

FPGA; Hardware Acceleration; Low-Power Circuits

Abstract

Digital circuit acceleration is pivotal in enhancing the performance and efficiency of modern electronic systems, particularly in applications such as real-time processing, low-power embedded devices, and high-speed data transmission. This article explores diverse methodologies to accelerate digital circuits, focusing on four core approaches. First, a Field-Programmable Gate Array (FPGA)-based functional verification framework is introduced. It leverages hardware-software co-verification and dynamic coverage analysis to achieve an 1132 × acceleration in verification cycles. Second, a reconfigurable architecture for regular expression engines is proposed, combining deterministic state machines and instruction-driven designs to optimize throughput and resource utilization. Third, a low-power multimode digital front-end circuit is developed using dynamic CIC filter configurations and Farrow structure optimizations, reducing power consumption by 11.9%, particularly in GSM and TD-SCDMA applications. Lastly, Tiny YOLO hardware acceleration on Zynq SoCs employs network pruning and pipeline parallelism, enabling real-time vehicle detection at 24 FPS, which is vital for autonomous driving systems. Additionally, computer vision architectures and SVM-based predictive models are analyzed for their roles in system optimization. These advancements collectively address critical challenges in speed, energy efficiency, and adaptability, offering significant value for both academic research and industrial applications in embedded systems and beyond.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Boyang Wu
PY  - 2025
DA  - 2025/10/23
TI  - Digital Circuit Acceleration Techniques for Computer Vision Tasks
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 149
EP  - 156
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_16
DO  - 10.2991/978-94-6463-864-6_16
ID  - Wu2025
ER  -