Digital Circuit Implementation of Artificial Neural Network Accelerator

DOI

10.2991/978-94-6463-864-6_15How to use a DOI?

Keywords

FPGA; Neural Network; Digital Circuit; Accelerator

Abstract

This paper provides a comprehensive review of digital circuit implementations for artificial neural network (ANN) accelerators, focusing on Solution types include Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA). It examines key optimization techniques such as precision-variable arithmetic logic units (ALUs), efficient dataflow management, and sparsity exploitation. These techniques aim to enhance computational throughput, energy efficiency, and latency in DNN processing. The survey highlights the advantages of FPGA-based accelerators, such as significant speed and energy efficiency improvements over GPUs through software-hardware co-design. However, it also discusses challenges like low-bit quantization and scalability. Additionally, the paper explores analog neural network implementations, emphasizing their potential for parallel processing and energy efficiency, while addressing accuracy and error resilience concerns. Case studies of FPGA-based DNN accelerators demonstrate practical applications, such as binarized weight optimization and parallel fast filtering algorithms, achieving high performance and recognition accuracy. The review concludes by identifying gaps in current technologies and suggesting future research directions to bridge the divide between theoretical potential and practical implementations in ANN acceleration.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Yukuan Zhao
PY  - 2025
DA  - 2025/10/23
TI  - Digital Circuit Implementation of Artificial Neural Network Accelerator
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 142
EP  - 148
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_15
DO  - 10.2991/978-94-6463-864-6_15
ID  - Zhao2025
ER  -