Memory Bitcells: Research on Structures, Performance, Challenges and Innovation Trends

DOI

10.2991/978-94-6463-864-6_39How to use a DOI?

Keywords

Memory bitcell; Circuit architecture; Performance optimisation; Emerging trends; Memory types

Abstract

This paper comprehensively investigates bitcell architectures in traditional and emerging memory technologies, including SRAM, DRAM, NAND Flash, STT-MRAM, ReRAM, and FeRAM. As the foundational unit of memory systems, bitcell design critically influences key performance metrics such as density, speed, power efficiency, and reliability. This paper analyses each memory type’s classical circuit configurations, operational principles, and performance trade-offs. For instance, SRAM variants (6T, 8T, 9T) exhibit distinct stability-speed-area compromises; DRAM evolves from 1T1C to vertically integrated 2T0C structures to address scaling challenges; and NAND Flash balances density, cost, and endurance through 3D stacking. Additionally, this paper highlights recent advancements, such as Intel’s RibbonFet-based SRAM and vertical STT-MRAM architectures, while concluding future research directions: enhancing stability, minimizing power consumption, optimizing area efficiency, and improving noise immunity. This work provides a systematic reference for advancing next-generation memory technologies.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Shiqi Li
PY  - 2025
DA  - 2025/10/23
TI  - Memory Bitcells: Research on Structures, Performance, Challenges and Innovation Trends
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 410
EP  - 427
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_39
DO  - 10.2991/978-94-6463-864-6_39
ID  - Li2025
ER  -