Investigation of Stt-Mram Technology based on Finfet Process

DOI

10.2991/978-94-6463-864-6_40How to use a DOI?

Keywords

Emerging Non-Volatile Memoey; Finfet; Stt-Mram; Low-Power Design

Abstract

This paper summarises the research progress and challenges of STT-MRAM technology based on FinFET technology, exploring its core advantages in high-density, low-power, and non-volatile storage. The advantage of FinFET mainly lies in its 3D gate. This paper summarizes relevant papers in recent years, focusing on bit cell structure optimization, adaptive write circuit design, and peripheral circuit coordination. It reveals how FinFET and spintronic device integration breaks traditional storage tech bottlenecks. This paper also compares it with other new storage techs, STT-MRAM’s high read speed and low power consumption are highlighted. It also foresees the collaborative innovation of FinFET and STT-MRAM for next-gen non-volatile memory, providing a theoretical framework for future research.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Zhihan Li
PY  - 2025
DA  - 2025/10/23
TI  - Investigation of Stt-Mram Technology based on Finfet Process
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 428
EP  - 438
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_40
DO  - 10.2991/978-94-6463-864-6_40
ID  - Li2025
ER  -