Comparative Analysis of Carbon Nanotube Field Effect Transistor Implementation of Flip-flop with MOSFET based design featuring Modern Low Power Digital VLSI Systems

DOI

10.2991/978-94-6463-754-0_52How to use a DOI?

Keywords

Flip-flop; Low power; Delay; CNTFET; MOSFET

Abstract

Presently, the design of power efficient memory elements like latches and flipflops for low power VLSI Systems are very challenging task. Transitionally the memory elements are designed by MOSFETs using NMOS and CMOS technologies under micrometer process. Even though the MOSFET based design results desired performance, that is not suitable for deep submicron technologies due to leakage and short channel effects. Devices based on graphene are gaining a lot of attention because of its superior electrical and scaling properties. Significant improvements over traditional MOSFETs are provided by graphene-based devices such as Carbon Nanotube Field-Effect Transistors (CNTFETs), particularly in deep submicron technologies under nanoscale. In this work, to analyze the significances of CNTFET based design compared with MOSFET based implementation, the flipflop named Pass transistor logic based implicit pulsed – dual edge triggered flipflop (PTIP-DETFF) designed by using MOSFETs under 120nm technology is taken into account. The topology of PTIP-DETFF is realized by using P-Type and N-Type CNTFETs under 32nm nanoscale technology. The key performance features such as total power consumption and input-data to output delay are recorded for both MOSFET and CNTFET implementation. The optimization features such as Power Delay Product (PDP), Energy Delay Product (EDP) and Power Energy Product are also noted. The CNTFET implementation of PTIP-DETFF consumes the average power consumption of 2.02µW and delay of 14.6 pS.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - P. Nagarajan
AU  - N. Ashok Kumar
AU  - C. Venkataramanan
AU  - P. Kabilamani
AU  - K. P. Porkodi
AU  - C. Kanmani Pappa
PY  - 2025
DA  - 2025/06/30
TI  - Comparative Analysis of Carbon Nanotube Field Effect Transistor Implementation of Flip-flop with MOSFET based design featuring Modern Low Power Digital VLSI Systems
BT  - Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)
PB  - Atlantis Press
SP  - 593
EP  - 606
SN  - 2589-4943
UR  - https://doi.org/10.2991/978-94-6463-754-0_52
DO  - 10.2991/978-94-6463-754-0_52
ID  - Nagarajan2025
ER  -