Implementation of Modified Booth-Wallace Tree Multiplier For Image Processing

DOI

10.2991/978-94-6463-754-0_24How to use a DOI?

Keywords

Multiplier; Booth Encoder; Booth Selector; Wallace Tree Multiplier

Abstract

In many different applications, multiplication is probably the most common arithmetic operation, including multimedia processing. Many digital systems depend on multipliers, however, because of their resource, energy, and critical path latency requirements, multipliers also present difficulties. In digital circuits, multiplication is a fundamental function. To balance speed, area, and power, multipliers must be designed efficiently. Modern processors and DSP applications benefit from techniques like Booth encoding, Wallace Tree reduction, and compressor based addition. This paper presents a combination of the Booth Multiplier with the Wallace tree multiplier to overcome the challenges. Modified Booth-Wallace Tree Multiplier efficiently enhances speed, power, and area by combining Booth encoding and Wallace tree reduction resulting in High-speed applications. The suggested multiplier is implemented using Booth Encoder, Booth selector, Full adder, and Half adder. A Booth encoder and selector are used in the Booth algorithm to generate partial products, which are then reduced by the Wallace tree multiplier utilizing full and half adders in five steps. The reduced products are then added together using a Ripple Carry Adder to produce the final output. The achieved power is 43.974W and the number of LUTs is 438 which is a lower area. The proposed Multiplier attained low power and area using Xilinx Vivado.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Julapalli Shainy Sithara
AU  - A. Alfred Kirubaraj
AU  - S. Senith
PY  - 2025
DA  - 2025/06/30
TI  - Implementation of Modified Booth-Wallace Tree Multiplier For Image Processing
BT  - Proceedings of the 2025 International Conference on Advanced Research in Electronics and Communication Systems (ICARECS-2025)
PB  - Atlantis Press
SP  - 258
EP  - 273
SN  - 2589-4943
UR  - https://doi.org/10.2991/978-94-6463-754-0_24
DO  - 10.2991/978-94-6463-754-0_24
ID  - Sithara2025
ER  -