Hybrid Carry Adder Design With Ripple And Ling Structures For Optimized Delay And Area

DOI

10.2991/978-94-6463-858-5_170How to use a DOI?

Keywords

Hybrid Carry Adder; Ripple Carry; Ling Carry; Low Power; Area Optimization

Abstract

The increasing demand for high-performance, low-power digital systems has highlighted the need for more efficient arithmetic units, particularly adders, which are vital components in processors and various digital circuits. Traditional adder designs, like ripple-carry and Ling adders, face challenges in balancing simplicity, area, and speed, especially as semiconductor technology continues to advance to smaller process nodes. Ripple-carry adders are simple but slow due to their linear carry propagation, while Ling adders offer improved speed but at the cost of increased complexity and area. This paper introduces a new hybrid carry adder design intended to improve digital circuit efficiency. The proposed adder combines a ripple-carry structure for the lower-order bits with a Ling-based parallel prefix structure for the higher-order bits, achieving a balance between simplicity and performance. The low-order sum calculation avoids complex carry look ahead, simplifying the design, while the high-order bits are processed by the Ling structure to reduce critical path delays. To further optimize efficiency, intermediate variables are introduced to facilitate Shannon expansion for better sum implementation. Additionally, the design ensures that the control signal for the output multiplexer (MUX) is synchronized with the input signals to avoid timing issues. The proposed adder will be validated across different semiconductor technologies, including 180nm CMOS processes, and assessed for key performance metrics such as area, power, power-delay product, and speed. This hybrid design will be compared with traditional Ling adders to demonstrate improvements in area efficiency, power consumption, and overall speed.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - R. Sireesha
AU  - E. Ashokkumar
AU  - J. Jayavardan
AU  - CH. Swetha
AU  - M. Uday Kiran
PY  - 2025
DA  - 2025/11/04
TI  - Hybrid Carry Adder Design With Ripple And Ling Structures For Optimized Delay And Area
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2043
EP  - 2051
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_170
DO  - 10.2991/978-94-6463-858-5_170
ID  - Sireesha2025
ER  -