Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

<Previous Article In Volume
Next Article In Volume>

FPGA Implementation Of An Improved Watchdog Timer For Safety-Critical Applications

Authors
Dodle Supraja1, Manoj Kumar1, *, S. V. S. Prasad1
1Department of ECE, MLR Institute of Technology, Hyderabad, Telangana, India
*Corresponding author. Email: dr.manojkumar@mlrinstitutions.ac.in
Corresponding Author
Manoj Kumar
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_202How to use a DOI?
Keywords
FIR; Xilinx; FPGA; Watchdog Timer; Simulation
Abstract

Embedded systems used in safety-critical applications demand the highest level of reliability. To ensure continuous operation and automatic recovery from runtime failures, external watchdog timers are commonly employed. However, most conventional watchdog timers require additional circuitry for timeout adjustments and offer limited functionality. This paper presents the design and architecture of an advanced configurable watchdog timer suitable for safety-critical applications. The proposed watchdog integrates multiple fault detection mechanisms, enhancing its robustness and reliability. Its functionality is designed to be versatile, making it applicable for monitoring any processor-based real-time system. Additionally, this paper discusses the implementation of the watchdog timer on a Field Programmable Gate Array (FPGA), ensuring adaptability to various applications while minimizing overall system costs. The efficiency of the proposed watchdog timer is evaluated through simulation analysis, followed by real-time hardware validation, where faults are deliberately introduced via software during processor execution. The results confirm the watchdog’s effectiveness in detecting and responding to system faults, reinforcing its suitability for high-reliability applications.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

<Previous Article In Volume
Next Article In Volume>
Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_202How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - Dodle Supraja
AU  - Manoj Kumar
AU  - S. V. S. Prasad
PY  - 2025
DA  - 2025/11/04
TI  - FPGA Implementation Of An Improved Watchdog Timer For Safety-Critical Applications
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2421
EP  - 2434
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_202
DO  - 10.2991/978-94-6463-858-5_202
ID  - Supraja2025
ER  -