Design and Validation of Low Power and High Efficient 2x4 Decoder with CMOS Technology

DOI

10.2991/978-94-6463-858-5_237How to use a DOI?

Abstract

Using a combination of static complementary metal-oxide semiconductor (CMOS), transmission gate logic, and pass transistor dual-value logic, this short presents a mixed-logic design strategy for line decoders. We provide two new topologies for the 2-4 decoder: one with 14 transistors to reduce power consumption and transistor count, and another with 15 transistors to maximize power-delay performance. Each scenario makes use of both normal and inverted decoders, resulting in four unique architectures in all. In contrast to their traditional CMOS equivalents, all IMPLEMENTED decoders are capable of full swinging and use a lower number of transistors. In conclusion, several 90 nm comparisons between DSCH and micro wind simulations reveal that the IMPLEMENTED circuits provide a considerable gain in power and latency, surpassing CMOS in almost every instance.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Ravali Sailla
AU  - L. Jagadeesh Naik
PY  - 2025
DA  - 2025/11/04
TI  - Design and Validation of Low Power and High Efficient 2x4 Decoder with CMOS Technology
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2826
EP  - 2832
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_237
DO  - 10.2991/978-94-6463-858-5_237
ID  - Sailla2025
ER  -