Design and Verification of Low Power High Performance of Hybrid Full Adder Using 32nm FINFET Technology

DOI

10.2991/978-94-6463-858-5_236How to use a DOI?

Abstract

Every kind of processor relies on full adders in their design and development. An area-efficient full adder with a small number of transistors is shown in this project. It is designed to be both powerful and power-efficient. In this paper, we present the design of a low-power full adder with good performance, detail its implementation as a 32-bit ripple carry adder, and compare it to other full adders that have been created in the past. The circuit for a low-power, high-performance full adder has been developed and simulated using the Tanner EDA tool. By reducing the high power consumption and increasing the speed significantly, the results demonstrate that the suggested high-performance low-power full adder is an efficient full adder cell with the least number of MOS transistors. These terms are associated with XOR gates, low power, full adders, and very large scale integration (VLSI). The following is the proper way to cite this paper: An article titled “Design of high- performance low-power full adder” was published in 2014 by Nehru and Shanmugam. Additionally, he was named the year’s finest master’s student. He is now a doctoral candidate at India’s Anna University’s Faculty of Electronics and Communication.

The fields of low power VLSI, VLSI circuit testing, FPGA design, VLSI computer-aided design (CAD), and signal processing are his primary areas of interest in the academic community. Several prestigious international periodicals have published his writings on these subjects. At Madras University in Coimbatore, A. Shanmugam earned a Bachelor of Science degree in 1972 from the Department of Electronics and Communication. The next year, in 1978, he earned a Master’s degree from Madras University’s Department of Electronics and Communication. At India’s Bharathiyar University’s Faculty of Electronics and Communication, he earned a doctorate in 1994. From 1972 to 1976, he was employed as a testing engineer at the Test and Development Center in Chennai, India. Between the years 2002 and 2004, he served as a professor and head of the electronics and communication department in India. The Bannari Amman Institute of Technology in India is his current place of employment as principal. He is a prolific journal reviewer and has written over a hundred articles in peer-reviewed publications throughout the globe. He has been a professor and businessman for over 40 years. His primary research is on image processing, signal processing, computer networks, and very large scale integration.

Copyright

© 2025 The Author(s)

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TY  - CONF
AU  - Pusuluri Jyothi
AU  - M. Satyanarayana
PY  - 2025
DA  - 2025/11/04
TI  - Design and Verification of Low Power High Performance of Hybrid Full Adder Using 32nm FINFET Technology
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2820
EP  - 2825
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_236
DO  - 10.2991/978-94-6463-858-5_236
ID  - Jyothi2025
ER  -