Design and Implementation Of 20T Hybrid Full Adder For Low Power High Performance Computing

DOI

10.2991/978-94-6463-858-5_212How to use a DOI?

Keywords

Pass-Transistor Logic; Arithmetic Units; Power Consumption; 45 nm technology

Abstract

The increasing requisition of low power and advanced computing architectures has driven the demand for efficient arithmetic units, particularly in digital circuits like Adders. The primary concern being dealt with here is the need to reduce power consumption while providing high computational performance in adder circuits, which are a key component of most computing systems. In order to address this issue, we present a new 20-transistor(20T) hybrid full adder circuit. The circuit utilizes a hybrid of complementary and pass-transistor logic styles, with the intent of finding a balance between performance and power efficiency. The 45nm CMOS technology node can be chosen to realize this circuit because of its ability to consume less power and switch at higher speeds relative to previous-generation technologies. Hybrid logic methods will be introduced, which are predicted to minimize transistor count and switching activity and bring about tremendous power savings without the loss of speed. This paper presents the design and implementation of a novel 20- Transistor (20T) Hybrid Full Adder using 45nm CMOS Technology. This design incorporates an XOR-XNOR circuit, which yields improved performance, and reduced propagation delay ultimately resulting in a more efficient and reliable digital system. Simulation results indicate a significant reduction in Power-Delay Product (PDP) and reduced worst-case propagation delay compared to existing designs. The enhancements made to the proposed adder make it an ideal candidate for applications requiring Low-power and High-Performance computing, enabling efficient and reliable processing in demanding digital systems.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - J. Leela Mahendra Kumar
AU  - B. Jahnavi
AU  - K. Prasanthi
AU  - S. Abdul Kalam
AU  - K. Pavan Kumar
PY  - 2025
DA  - 2025/11/04
TI  - Design and Implementation Of 20T Hybrid Full Adder For Low Power High Performance Computing
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2550
EP  - 2563
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_212
DO  - 10.2991/978-94-6463-858-5_212
ID  - Kumar2025
ER  -