Asynchronous FIFO in FPGA for Video Acquisition in IoT Based Systems

DOI

10.2991/978-94-6239-628-9_3How to use a DOI?

Keywords

FPGA; FIFO; Dual Clock; Video Processing; IoT

Abstract

The acquisition of uncompressed video streams over Ether- net on FPGA platforms constitutes a substantial design challenge, primarily due to real-time bandwidth requirements and the susceptibility of packet-based transmission to jitter and synchronization errors. FIFO buffers have a critical role in FPGA-based Systems, where clock mismatching and bursty data streams can otherwise lead to loss of data or synchronization error. Their ability to decouple write and read operations, while maintaining continuous data throughput, makes them particularly valuable in video pipelines where uninterrupted pixel flow is critical. Recent advances in low-power and clock-gated FIFO architectures further reinforce their suitability for high-performance, real-time processing applications. Transmitting a 640 × 480 @ 30 FPS RGB video stream requires approximately 295 Mbps, which lies well within the capacity of Gigabit Ethernet (1 Gbps). However, the stream remains vulnerable to jitter and packet delay variations. To address this, we propose a Dual-Clock FIFO architecture implemented on FPGA. In the proposed design, Ethernet payloads arriving at 125 MHz are decoded into a 32-bit RGB stream and written to the FIFO, while the read domain operates at a higher frequency range of 175 MHz. This design choice provides a FIFO depth of 4 KB, corresponding to the buffering of approximately one video line, to absorb jitter and ensure alignment preservation. Simulation results conducted in AMD Vivado 2024.1 confirm stable clock- domain transfer, precise RGB reconstruction, and negligible frame loss even under worst-case burst conditions. These findings demonstrate the feasibility and effectiveness of the proposed FIFO-based design for enabling reliable, real-time video acquisition and processing in FPGA video pipelines.

Copyright

© 2026 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Arpan Konar
AU  - Lakshay Balani
AU  - Debiprasad Priyabrata Acharya
PY  - 2026
DA  - 2026/03/31
TI  - Asynchronous FIFO in FPGA for Video Acquisition in IoT Based Systems
BT  - Proceedings of the International Conference on Recent Trends in Intelligent Computing, Manufacturing, and Electronics (rTIME 2025)
PB  - Atlantis Press
SP  - 18
EP  - 27
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6239-628-9_3
DO  - 10.2991/978-94-6239-628-9_3
ID  - Konar2026
ER  -