Exploring Low Power Parallel Prefix Adder Using Non-Conventional Logic Styles in Terms of Scaling Parameters

DOI

10.2991/978-94-6463-940-7_25How to use a DOI?

Keywords

Low Power VLSI; Ladner-Fischer Adder; Pass Transistor Logic (PTL); Double Pass Transistor Logic (DPTL); Gate Diffusion Input (GDI); Energy- Performance-Area (EPA); Parallel Prefix Adders; DSCH3; Microwind 3.1

Abstract

The demand for faster and energy- efficient arithmetic circuits continues to grow with the rise of modern VLSI applications. This paper explores a 4- bit Ladner-Fischer Parallel Prefix Adder (LF-PPA) implemented using non- conventional logic techniques such as Pass Transistor Logic (PTL), Double Pass Transistor Logic (DPTL), and Gate Diffusion Input (GDI). The proposed designs are analyzed in terms of power usage, silicon area, and layout efficiency, with simulations performed using DSCH3 and layouts generated in Microwind 3.1. Simulation outcomes demonstrate that the GDI-based approach yields the most compact area, whereas DPTL achieves the lowest power dissipation. These findings underline the trade-offs between compactness and energy efficiency. Although the prototype is limited to a 4-bit design, the results provide useful insights into how these logic styles may be extended to wider adders in large-scale integration, DSP units, and energy-conscious VLSI architectures. Overall, this study highlights comparative design perspectives for developing optimized prefix adders in advanced digital systems.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - K. Srilatha
AU  - Avala Mallikarjuna Prasad
PY  - 2025
DA  - 2025/12/31
TI  - Exploring Low Power Parallel Prefix Adder Using Non-Conventional Logic Styles in Terms of Scaling Parameters
BT  - Proceedings of the Conference on Social and Sustainable Innovation in Technology & Engineering (SASI-ITE 2025)
PB  - Atlantis Press
SP  - 342
EP  - 350
SN  - 1951-6851
UR  - https://doi.org/10.2991/978-94-6463-940-7_25
DO  - 10.2991/978-94-6463-940-7_25
ID  - Srilatha2025
ER  -