Energy-Efficient Design and Delay Optimization of a Absolute-Value Detector

DOI

10.2991/978-94-6463-864-6_34How to use a DOI?

Keywords

Absolute-Value Detector; Hybrid Logic; Logical Effort; Propagation Delay

Abstract

With the rapid development of digital integrated circuits, absolute value detectors have become indispensable devices in signal processing, control systems, arithmetic operations and other fields. This paper presents an optimal design for a 4-bit absolute value detector with a focus on reducing latency and power consumption using mixed logic methods and logical effort analysis. The circuit combines static CMOS logic for control and through-tube logic (PTL) for data processing to achieve energy efficiency and high speed. XOR gates, full adders, and multiplexers are used to perform conditional inversion and 2’s complement operations based on sign bits. A three-input comparator is integrated into the same logical stream, minimizing redundancy and area. Critical path analysis and gate sizing with logical effort help minimize propagation delays and improve timing performance. Logic simplification through the Carnot map also reduces the complexity of the circuit. The final design proves the balance between speed, precision and energy efficiency, making it ideal for modern VLSI systems. This research provides a practical framework for efficient digital design and opens up possibilities for future enhancement using advanced technologies such as finfet, CNTs or 2D materials.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Feihan Li
PY  - 2025
DA  - 2025/10/23
TI  - Energy-Efficient Design and Delay Optimization of a Absolute-Value Detector
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 352
EP  - 361
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_34
DO  - 10.2991/978-94-6463-864-6_34
ID  - Li2025
ER  -