Systematic Analysis and Design of a Four-Bit Absolute Value Comparator

DOI

10.2991/978-94-6463-864-6_33How to use a DOI?

Keywords

Logic Effort; Circuit Design; Delay Reduction; Size Optimization; Energy Consumption Optimization

Abstract

This paper is dedicated to the design of a 4 - bit absolute value comparator, aiming to resolve its power consumption issue. Initially, the logic effort method is employed to analyse the circuit structure, precisely identify the critical path, and optimize the sizes of devices on it to achieve the minimum delay state. Subsequently, by adjusting voltage parameters and fine - tuning device sizes, the balance between power consumption and performance is thoroughly explored. Experimental results reveal that when only the voltage is adjusted, with the delay extended to 1.5 times the original, the power consumption can be decreased to 60.84% of the original. Optimizing only the capacitor size can reduce the power consumption to 60.73% of the original under the same delay condition. The combined optimization of voltage and capacitor size is even more effective, reducing the power consumption to 51.42% of the original. This “performance - for – efficiency” strategy is highly applicable in low - power embedded systems. Future research could focus on the synergistic adjustment of other circuit parameters to further optimize the performance - power trade - off.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Lanrui Wang
PY  - 2025
DA  - 2025/10/23
TI  - Systematic Analysis and Design of a Four-Bit Absolute Value Comparator
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 340
EP  - 351
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_33
DO  - 10.2991/978-94-6463-864-6_33
ID  - Wang2025
ER  -