Design of Absolutely-Value Detector and Optimize its Delay and Power Consumption

DOI

10.2991/978-94-6463-864-6_32How to use a DOI?

Keywords

Integrated Circuit; Energy Consumption; Optimal Delay; Transmission Gate; Logic Effort

Abstract

With the development of electronic products, integrated circuits have become the focus of research in related fields. In this paper, a 4-bit absolute value detector with low delay and low energy consumption is designed, which is composed of adder, MUX and comparator. When the circuit is working, MUX is used to screen the positive and negative of the 4-bit input signal, the adder converts the negative number into the corresponding absolute value, and transmits the absolute value signal to the comparator through MUX and compares it with the given threshold, and finally outputs the result. Based on the linear delay model, the logical effort and parasitic delay of the circuit are calculated, and the MUX part of the circuit is composed by a transmission gate. Through some calculation and optimization, the optimal delay of the detector is 44.76. By adding a certain delay, the delay reaches 67.14 of the 1.5x optimal delay, and the power consumption of the circuit reaches the optimal 9.72C. Finally, this paper realizes a relatively simple 4-bit absolute value detection circuit with fewer components, which greatly improves the performance of the circuit. This research also has some reference value for the design of related circuits.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Zhizheng Wang
PY  - 2025
DA  - 2025/10/23
TI  - Design of Absolutely-Value Detector and Optimize its Delay and Power Consumption
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 320
EP  - 339
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_32
DO  - 10.2991/978-94-6463-864-6_32
ID  - Wang2025
ER  -