Design and Optimization of an Absolute-Value Detector in Vlsi Systems

DOI

10.2991/978-94-6463-864-6_36How to use a DOI?

Keywords

Vlsi Systems; Static Cmos; Pass-Transistor Logic

Abstract

Because digital systems are developing rapidly, efficient arithmetic components are needed, especially absolute value detectors and arithmetic logic units (ALUs) for signal processing. However, the traditional design based on Complementary metal-Oxide-semiconductor (CMOS) has many limitations in terms of power and the number of transistors, which prompts people to attempt to explore the hybrid architecture of static CMOS and through-tube logic (PTL). This paper proposes a 4-bit absolute value detector that combines the algorithm efficiency of PTL and the robust control optimization of CMOS. This design maintains scalability, achieves lower latency and power consumption, minimizes the size of the gate and the logical effort used by the Carnot diagram logic. Compared with traditional methods, this method significantly highlights its potential in high-speed and low-power applications. Adaptive transistor size, emerging nanodevices and other technological fields are all key directions for future work using this method.The CMOS-PTL hybrid 4-bit detector achieves performance optimization through logical minimization, paving the way for the next-generation very large-scale integration (VLSI) systems with higher speed and efficiency, and supporting the multi-domain integrated development of new products.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Xiang Zhan
PY  - 2025
DA  - 2025/10/23
TI  - Design and Optimization of an Absolute-Value Detector in Vlsi Systems
BT  - Proceedings of the 2025 2nd International Conference on Electrical Engineering and Intelligent Control (EEIC 2025)
PB  - Atlantis Press
SP  - 378
EP  - 387
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-864-6_36
DO  - 10.2991/978-94-6463-864-6_36
ID  - Zhan2025
ER  -