Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)

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Design And Implementation of Hybrid Memory Logic Built-In Self-Test Architecture

Authors
Chokkakula Ganesh1, *, A. Murali2, L. Dharma Teja1, N. Shivani1, B. Shailaja1, R. Anand1
1Deptartment of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India
2Department of Electronics and Communication Engineering, QIS College of Engineering & Technology, Ongole, AP, India
*Corresponding author. Email: Ganesh_ch@vnrvjiet.in
Corresponding Author
Chokkakula Ganesh
Available Online 4 November 2025.
DOI
10.2991/978-94-6463-858-5_163How to use a DOI?
Keywords
HML-BIST; area; Latency; Power
Abstract

BIST (Built-in Self-test) modules are an intrinsic part of many applications like microprocessors, micro controllers, multi-processor system and multicore system. The problems in different memory systems affected by stuck-at faults cannot be solved using the standard Built-In Self-Test (BIST) modules. Accordingly, the main objective of this research is to build a Hybrid Memory Logic (HML)-BIST for identifying and correcting memory component faults. Random test patterns of write, read and write data were generated at the beginning with the use of linear feedback shift register (LFSR) modules. It is then input into the LFSR in order to generate random numbers using an activity factor so it will not repeat. After that, the space comparator will appear to compare what is stored in memory with data from their original sources. For various test scenarios, memory correction is performed by the BIST module. The simulations showed that when compared to previous methods, the new HML-BIST method produced better results in terms of power, area, and latency.

Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Volume Title
Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
Series
Advances in Computer Science Research
Publication Date
4 November 2025
ISBN
978-94-6463-858-5
ISSN
2352-538X
DOI
10.2991/978-94-6463-858-5_163How to use a DOI?
Copyright
© 2025 The Author(s)
Open Access
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Cite this article

risenwbib
TY  - CONF
AU  - Chokkakula Ganesh
AU  - A. Murali
AU  - L. Dharma Teja
AU  - N. Shivani
AU  - B. Shailaja
AU  - R. Anand
PY  - 2025
DA  - 2025/11/04
TI  - Design And Implementation of Hybrid Memory Logic Built-In Self-Test Architecture
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 1963
EP  - 1981
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_163
DO  - 10.2991/978-94-6463-858-5_163
ID  - Ganesh2025
ER  -