A Survey and Verification of Low Power Design Techniques Suitable for FPGA design

DOI

10.2991/978-94-6463-831-8_48How to use a DOI?

Keywords

FPGA; low power; energy efficient; ASIC

Abstract

This paper provides a review on low power design techniques for Field Programmable Gate arrays (FPGAs). Application of each technique is targeted towards portable devices required for day-to-day life. It also provides recent trends and techniques for low power devices. It mentions the future work for application of low power and energy efficient devices. The survey has been supported by applying low power design techniques considering combinational logic design of 4- bit up down counter for verification of techniques. Counter design is considered as the best example due to the happening of continuous switching activities. It has been verified that for counter like example, when applied with FPGA based low power design techniques, lowest power consumption is possible using data retention technique whereas maximum power is consumed using clock and power domain partitioning as well as voltage island method. It is also verified that the average power is consumed using methods such as clock gating and power gating.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Mrinalini Joshi-Pangaonkar
AU  - Pratibha P. Shingare
PY  - 2025
DA  - 2025/08/31
TI  - A Survey and Verification of Low Power Design Techniques Suitable for FPGA design
BT  - Proceeding of the 1st International Conference on Lifespan Innovation (ICLI 2025)
PB  - Atlantis Press
SP  - 395
EP  - 402
SN  - 2468-5739
UR  - https://doi.org/10.2991/978-94-6463-831-8_48
DO  - 10.2991/978-94-6463-831-8_48
ID  - Joshi-Pangaonkar2025
ER  -