Design and Optimization of FPGA-Based Vending Machine

DOI

10.2991/978-94-6463-787-8_8How to use a DOI?

Keywords

Verilog; FPGA; Zed board; Vending machine; RTL design

Abstract

This paper presents the Register Transfer Level (RTL) design logic of the vending machine and its implementation on the Field Programmable Gate Array (FPGA) zed board. FPGA technology enables faster processing, reconfigurability, and better resource efficiency for vending control. The FPGA-based approach provides a modern, adaptable, high-performance vending machine automation solution. The Control logic in this proposed vending machine model includes insertion of amount, cancel operation, and dispensing of candy. The proposed design is tested and simulated using the Xilinx Vivado 2024 version, achieving a 69.3% power optimization than the previous model, with further power consumption and timing analysis performed across different RTL coding styles like if-else, switch case, and while loop implementations.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Rajan Singh
AU  - Krishna Sai
AU  - Manish Reddy
AU  - Yaswanth Kalyan
AU  - Rushith Pendela
AU  - Shrikant Upadhyay
PY  - 2025
DA  - 2025/07/17
TI  - Design and Optimization of FPGA-Based Vending Machine
BT  - Proceedings of the Recent Advances in Artificial Intelligence for Sustainable Development (RAISD 2025)
PB  - Atlantis Press
SP  - 77
EP  - 87
SN  - 1951-6851
UR  - https://doi.org/10.2991/978-94-6463-787-8_8
DO  - 10.2991/978-94-6463-787-8_8
ID  - Singh2025
ER  -